1. Field of the Invention
The present invention relates to a semiconductor memory, in particular, to an input circuit which receives an external control signal such as a WE (write enable bar) signal.
2. Description of the Related Art
A semiconductor memory device provides an input circuit which is connected to a reference potential line connectable to an external power source and which provides a MOS transistor receiving an external control signal such as a WE (a write enable bar) signal at a TTL level. The input circuit outputs an inverted MOS level signal in accordance with a high level or a low level of the external control signal. The semiconductor memory device further provides an output stage transistor which is connected to the reference potential line and which generates a low or high level output by turning the output stage to ON.
The external control signal of the semiconductor memory device, signals such as RAS (Row address strobe), CAS (Column address strobe), OEand WE having a TTL level, are used for controlling the mode or timing of operation of the internal circuit in the device. Memory cells are accessed by receiving these signals and address signals, and read and write operations are carried out for the memory cells. The present invention is concerned with the input circuit for these external control signals, particularly the WE signal. This input circuit, which receives the TTL level signal supplied to an input terminal, has a high voltage level of 2.4 V or more and a low voltage level of 0.8 V or less and converts the same to a MOS level having a high level power source voltage V.sub.CC (5 V) or a low level power source voltage V.sub.SS (0 V). The input circuit activates a clock generator circuit for carrying out a specific operation mode by signals output after the level is converted.
When, for example, the WE signal is at a H (high) level, the memory is in a read-out mode, and data in the memory cell selected by address signals is read out externally.
In the circuit as mentioned above, when the output stage transistor is turned ON to make the output level low or high, a comparatively large current flows via the output stage transistor to or from the reference potential line. As the wire for forming the reference potential line has a resistance, then the potential level of the reference potential line rises or falls when the large current flows via the output stage transistor thereto or therefrom.
On the other hand, the TTL level input signal, for example the WE signal, has a constant level with respect to the external ground level, that is, lower than 0.8 V for the low level and higher than 2.4 V for the high level with reference to the external ground level. Thus, when the reference potential level inside the device, which should be held at the ground level, rises due to the large current at the output stage, the input stage transistor receiving an input of the TTL high level may not turn ON, so that the input circuit sometimes cannot output a low level output, as explained in detail hereinafter. When the output of the input circuit is not at the L level, a writing mode is operative, and it is possible for the writing circuit inside the device to operate and the memory carry out a write operation. Further, the writing circuit provides a latch function, and thus when the H level output is initially generated, it is latched and a writing error may occur.
When the input logic level is defined with respect to the reference potential level supplied by the high level power source voltage, unlike the above case, the falling of the potential at the reference potential line inside the device accompanied by the high level output at the output stage may cause a similar malfunction at the input stage.